20.3. SPECIAL CHARACTERISTICS OF MAGNETIC DRUM COMPUTERS

Sections 20.3 through 20.4.2 by William R. Arsenault.

Because the cost of storing information on magnetic drums is much less than for storing in other memories suitable for use on high-speed computers, it is possible to construct certain registers as part of the magnetic drum memory.

20.3.1. Buffer Memories. Placing two heads on the same track some number of sector lengths apart provides a lower-capacity memory than that of a full channel but with a proportionally lower access time. lf there are normally 100 sectors around the drum, then two heads spaced 10 sector lengths apart may he used to provide a 10-word capacity loop with an access time of one-tenth the access time to a track containing but one head.

A section of a drum rotating past two heads is depicted in Fig. 20.1. Information is read from one head, amplified, and stored for one bit time in a flip-flop. It is then recorded by a head set 10 sector spaces back along thc circumference (actually 10 sector spaces less one bit space).

As before, if the word is stored serial-serial, the sector length will be the same as the word length. If the storage is series-parallel, then as many of these loops as there are bits in parallel are needed to store the 10 words.

The access time to the loop is reduced since it requires only a fraction of a drum revolution for a particular bit of a word to appear in the output successive times. lf faster access is desired the heads may be spaced closer together. Some computers using this method of storage have several loops of different head spacing.

Since the information recorded is of interest only while it exists between the two heads, several other independent loops may be spaced around the circumference on the same track. The record head associated with the loop erases all information previously recorded on the track and inserts the new information. Therefore, information recorded by heads associated with other loops will not interfere with each other.

The loop may be addressed in a manner similar to any read-record head. The head is selected and a coincidence with a sector address is obtained.


Fig. 20.1. Recirculating register.

20.3.2. Circulating Registers. Information contained in a register is not used until it appears at the end of the register, i.e., as it is shifted out. In a serial-binary machine addition may be performed by adding the least significant bits of the two operands, then shifting and adding the next two significant bits. The process continues until the two words are added together.

This operation can be made to take place at the machine clock rate and in synchronism with the machine word times. The same results may be obtained if the registers take the form of circulating loops on the drum. Instead of the head spacings being multiple word lengths apart, they now must be something less than one word length apart.

For such loops the two heads must he spaced very close together. For a machine with a word length of 40 bits and a bit density of 100 per inch, the heads must be spaced less than 0.40 in. apart. This puts a physical limitation on the size of the head; however, several are commercially available that can meet these specifications.

Putting the storage registers on the drum complicates the logical design of a computer but realizes great savings in equipment. For a serial-binary machine up to 80 per cent of the equipment associated with the shifting registers may he eliminated as compared with equivalent vacuum-tube or transistor registers.

20.3.3. Loop Realization and Machine Timing. Successful operation of circulating registers takes advantage of the complete synchronization that exists in a magnetic drum processor. Figure 20.2 depicts a section of a drum and schematically shows some logical elements associated with two tracks. The first, the accumulator, is a circulating-loop register, where two bits of the word contained circulate through static flip-flop storage. Normal information flow is from A101 to the record amplifier and back onto the drum. The second is an information track with a single head associated with it. The particular head is selected by addressing in a manner described in earlier sections.

The bits of the two words in question are shown in position at the beginning of a word time. Assume the command being executed calls for an addition of the word in the accumulator and the word N of the selected track. The record amplifier will be made to select and record the output of the binary adder. This output is the result of adding the bits contained in A101 and A200, the least significant bits of the respective words.

The b0 at the record head is then the first bit of the new word being generated by the add command. As the drum rotates under the head successive bits will be added and the results recorded in the accumulator. At the end of the word time the record amplifier again selects the output of A101 so that the accumulator word will recirculate.


Fig. 20.2. Arithmetic unit.

If it is desired to insert a new word into the accumulator from the memory, the record amplifier will select the output of A200 directly for the correct word time.

Again, at the beginning of a word time, b0 of the word on the information track appears in A200. This implies that this information, as it appeared on the drum, must have already passed under the head, been amplified, strobed, and set into A200. If it had been desired to record new information into word location N, then b0 must have already been recorded. It follows then that there is a one bit delay between reading and recording with the same head.

In order to send information from the accumulator to the memory, it is necessary to start the record operation one bit time earlier. This is the purpose of A100. When b0 appears in A100 the read-record head is in the correct position to record it. This type of compensation is not necessary when transferring information between several loops that may exist in a machine.

The binary adder shown in Fig. 20.2 is only part of the logical circuits that may exist. Such operations as compare, extract, etc., may all take place in a word time.

20.8.4. Shift Operations. The relative position of bits must he defined at a particular time when using these dynamic techniques. For purposes of discussion, this will be defined as the beginning of a word time. Thus b0 is in A101 at the beginning of a word time.

In order to shift information within a word it is necessary to shorten or lengthen the loop. If it is desired to shift left, the loop is lengthened 1 bit to 41 bits. This is accomplished by inserting A102 into the information flow. The bit b0, has 41 positions to assume but only 40 bit times to assume them. Therefore, at the beginning of the next word time, b0 will be in A100 or one bit space to the left. For each word time that the information is made to pass through A102, the respective bits will be one more position to the left.

In a like manner, information may be shifted right by shortening the loop, This is accomplished by passing A101. Now the loop is only 39 bit positions long and b0 will already be recorded back on the drum after one word time. The bit b0 will occupy the space formally [formerly?] occupied by b39.

The entire computer operation may be designed around this technique. The exception is when it is necessary to input or output to or from an asynchronous device, such as a tape punch. Here, some amount of buffer storage must be provided.

20.4. SOME GENERAL-PURPOSE DRUM COMPUTERS AND THEIR CHARACTERISTICS

20.4.1. The IBM 650. Memory. This machine uses a cobalt-nickel-plated drum, 4 in. in diameter and 14 in. in length. The drum rotates at 12,500 rpm. The recording density is 50 bits per inch, giving a machine pulse rate of 128,000 pps.

Digit
001100
111000
210100
310010
401010
500110
610001
701001
800101
900011

Fig. 20.3. Five-bit drum code.

Information is stored in at series-parallel form, 5 bits in parallel, representing a decimal digit. A word is 10 decimal digits long, plus a digit for sign. An additional space bit separates successive words. A word, then, occupies 5 tracks (referred to as a band) by 12 bits in the circumferential direction. Each band contains 50 words, and 40 bands give a capacity of 2,000 words.

The drum stores information in a 5-bit code shown in Fig. 20.3. This code can casily be checked for error since each decimal digit always contains two and only two binary 1's. The digits are converted between this code and a biquinary code when the word is transferred between the drum and the logical circuitry.

Word Structure. The machine word is 10 decimal digits long, plus sign. Information, when in the logic section, is carried in the word in the form of a 7-bit biquinary code.

When a word in the machine takes the form of a command the digit positions have the significance shown in Fig. 20.4. This is the so-called modified single-address code.


Fig. 20.4. Command word.

The two most significant digits define the operation that is to take place. There are 44 possible operations in the machine. The operand address part of the command word defines the address on the drum where data are to be found or sent. When an operation does not imply an operand address, this part of the word may take on one of the following meanings:

  1. Number of positions to bc shifted either right or left
  2. Address of a block of words in the memory to he output
  3. Address of a block of words where data are to be input
  4. Address of an alternative command, dependent upon certain tests
  5. Address of a word where a search operation is to start

The least significant four digits specify the address of the next command unless a branch is indicated (item 4 above).

Logic. The logical section of the computer consists of two registers, the distributor and the accumulator. In addition, there is the program register that holds the command.

These registers are based on capacitor storage and circulate continuously in synchronism with the drum, much as circulating registers discussed in Sec. 20.3.

The distributor acts as an intermediate storage link between the accumulator and memory. Any number transferred between the accumulator and the memory passes through the distributor.

The accumulator has a capacity of 20 digits. It is divided into two 10-digit halves; however, carries propagate between the lower and upper halves. A 10-digit operand may he added to the 20-digit accumulator to form a 20-digit sum. A 10-digit operand may be multiplied to form a 20-digit product, or divided to form a 10-digit quotient and 10-digit remainder.

The distributor and both halves of the accumulator are addressable as well as memory locations on the drum. This allows either half of the accumulator to be added to or subtracted from the other half; either half added to itself; the upper half to be multiplied by itself, i.e., squared; etc.


Fig. 20.5. Information-flow block diagram.

Among the many operations common to a general-purpose computer, the machine is capable of performing a table-look-up function. The argument is stored in the distributor and the location where the search is to start is given in the operand address. The machine then compares successive words on the drum with the word in the distributor, When the word in the memory becomes equal to or larger than the word in the distributor, the operation terminates and the address of the compared word is given in the accumulator. There are 50 words around the drum. lf no comparison is made by sector 48, the machine switches to the next band and searches that band, starting at the first sector. Sectors 49 and 50 are ignored in the search, and this time is used to switch bands.

Command Execution. Information flow within the computer takes place in a series- parallel fashion. All logical operations take place by passing the two operands serial by digit through the logic circuits. The word in the accumulator is merged with the operand word to form the desired results. The result is put back into the accumulator.

The registers of the machine circulate in a dynamic fashion, in synchronism with the drum timing. Since the accumulator is two word lengths long it takes two word times for information to circulate. Information in the lower accumulator is synchronized to enter the logic circuits during an even word time and thc upper accumulator during an odd word time.

Shifting is performed by shortening or lengthening the number of digit positions in the accumulator. To shift left, the accumulator is lengthened one digit position. Each circulation of the accumulator moves the digits one position. Thus, it takes two word times per bit position shifted to execute this part of the operation.

A typical add command takes 8 word times to execute, Assume that an add to lower accumulator command (AL) is located in memory address 0001. During this word time the command is gated from the drum into the program register. During word time 0002, the operation part of the command is sent to the operation register and the operand address is sent to address register. During word time 0003, the appropriate drum heads are selected. The machine then waits for the operand sector to pass under the heads.

If the operand is in one of the 40 word locations of sector 04, there will be no wait and the data word is sent to the distributor. It was stated that the lower part of the accumulator circulated in a manner such that it could enter the logic circuits only during an even word time. The machine must then wait until sector 06 to add the two numbers. The upper part of the accumulator passes by during sector 07 time. Meanwhile, the address of the next command is sent to the address register. It is therefore possible to locate the next command in one of the words at sector 09.

With the data at the optimum location the entire command requires 0.768 msec.

Multiply is carried out by repeated additions and shifts and requires from 20 to 200 word times to perform the arithmetic functions. Divide requires from 60 to 240 word times to perform the arithmetic.

Assuming random data and instructions the following times are quoted for command execution:

CommandAverage Time, msec
Add, subtract, store5.2
Shift2.8
Branch2.7
Multiply11.6
Divide14.5

Equipment. The processor is composed of some 2,000 tubes and 3,600 crystal diodes. Tube types used are the 5965, 6211, 12AY7, 6AL5, 2021, and 5687. The machine consumes 16 to 18 kva of power.

Auxiliary Equipment. Normal input and output are via punch card. A high-speed core storage of 60 words may be added. This storage is addressable from the processor and also acts as a buffer between the machine and magnetic-tape units. Up to 60 magnetic-tape units may be tied to the machine.

20.4.2. The Royal-McBee LGP-30. Memory. The drum memory is approximately 8 in, in diameter and 10 in. long. Words are stored in a pure serial form, 32 bits to the sector. The 64 sectors per track give a total track capacity of 2,048 bits.

The drum rotates at approximately 3,500 rpm, giving a bitrate of 120,000 per second.

There are 64 tracks to the main memory. This provides a total storage capacity of 4,096 words.

In addition to the storage above, there are three circulating registers. These are called the counter register, instruction register, and the accumulator. The registers operate as discussed in Sec. 20.3. Here it is required that the heads be spaced 31 bits. At a density nf 80 per inch, the head centers are approximately 0.4 in. apart.

Word Structure. The machine word is 30 bits long, plus a single bit for sign. A thirty-second bit is used as a space bit on the drum.

Information is carried in pure binary form with the decimal point considered ahead of the must significant bit. Numbers vary from +1 to -1 in increments of 2-30.

When the machine word is used as a command only 16 of the bits have significance. Four are used to define the operation and the remaining 12 define the address of the operand. This is referred to as a single-address command structure.

Order Code. The complete order code is included here as it represents a near minimum number of operations needed to perform problems conveniently on a general-purpose computer. The code is the four binary bits carried in the command word that define what operation is to be performed. An operand address is needed for each command word except for the last three commands in the list.

Logic. There are three registers in the machine used to carry out all logical operations. These three registers are circulating types where a majority of the information held in the registers is contained on the drum.

One circulating register is called the counter. It is one word length long and stores the address of the next command, As previously described, single-address machines usually obtain their commands from successive addresses. Each time this address is used it is augmented by one and held until it is used to designate the next command. This procedure continues until a transfer command inserts a new command address in the counter.

A second circulating register is called the instruction register. This normally holds the command word containing the instruction and operand address. For this purpose information is derived directly from the main drum storage.

Table 20.2. The LGP-30 Command List
INSTRUCTION ORDER LIST SHOWING CODE FOR EACH INSTRUCTION
CodeEffect
Arithmetic:
0001Bring, Clear the accumulator, and add the contents of location m to it
1110Add contents of m to the contents of thc accumulator, and retain the result in the accumulator
1111Subtract the contents of m from the contents of the accumulator, and retain the result in the accumulator
0111Multiply the number in the accumulator by the number in memory location m, terminating the result at 30 binary places
0110Multiply the number in the accumulator by the number in m, retaining the least significant half of the product
0101Divide the number in the accumulator by the number in memory location m, retaining the rounded quotient in the accumulator
1001Extract, or logical-product order -- i.e., clear the contents of the accumulator to 0 in those bit positions occupied by 0's in m
Transfer control:
1010Transfer control to m unconditionally -- i.e., get the next instruction from m
1011Test, or conditional transfer. Transfer control to m only if the number in the accumulator is negative i
Record:
1100Hold. Store contents of the accumulator in m, retaining the number in the accumulator
1101Clear. Store contents of the accumulator in m and clear the accumulator
0010Store only tho address part of the word in the accumulator in memory location m, leaving the rest of the word undisturbed in memory
0011Return address. Add 1 to the address held in the counter register C and record in the address portion of the instruction in memory location m. The counter register normally holds the address of the next instruction to be executed
Miscellaneous:
0100Input. Fill the accumulator from thc Flexowriter
1000Print a Flexowriter symbol. The symbol is denoted by the track number part of the address (x)
0000Stop. Contingent on five switch (T1 . . . T5) settings on the control panel

The third register is the accumulator. This register is one word length long for most operations. However, a second read head spaced an additional word length, plus a bit space, allows the register to be lengthened to 65 bits during certain portions of the multiply and divide operations.

The execution of a command is divided into eight steps or phases, For most operations only four are used.

In the first phase a search is made for the command word whose address is held in the counter register. That part of the address designating the track is sent to the track-selection register, comprised of six toggles, and a sector search is made on the remaining bits.

Upon sector coincidence the machine is set to phase 2 and the command word is read into the instruction register. This period always lasts a single word time.

Again during phase 3 a search is made, this time for the operand address. Upon sector coincidence the machine is set to phase 4.

Phase 4 lasts one word time and is the period when all logical and arithmetic operations take place, except for the multiply and divide orders. If the operation is addition, the word in the accumulator is added serially, bit by bit, to the word being read from the memory. If it is a send order, the word in the accumulator is recorded in the sector found during phase 3.

For a transfer order, the contents of the instruction register are sent to the counter register during phase 4. This, then, becomes the address of the next command, as required.

Phases 2 and 4 are each one word time long and phases l and 3, the search periods, are a minimum of one word time. Assuming the operand is located in the optimum position, these operations can be completed in four word times.

Multiplication. Multiplication is carried out by a series of additions and shifts. During phase 4, the multiplicand, which is specified by the operand address, is read from the memory into the instruction register. The multiplier, which already exists in the accumulator, continues to circulate. During the next two periods the product is formed. First, the accumulator is extended to 65 bits by reading from the second head rather than from the first. This lengthens the loop to slightly over 2 words in length. The effect of this is to precess the information held in the accumulator one bit position each two word times; i.e., the bits of the word are all shifted one position in the more significant direction each complete circulation.

The accumulator then holds the multiplier and the partial product. As the accumulator circulates, the rnultiplicand is added in or not, depending upon the value of the pertinent digits of the multiplier. This addition operation happens each full accumulator circulation. Also, the accumulator "shifts" one bit each circulation. The multiplicand is therefore added into a successively lesser significant part of the partial product.

The partial product is initially one word length long and progressively grows. As each digit of the multiplier is used it is dropped from recirculation. This compensating storage requirement allows the accumulator to handle both pieces of information while it is extended to two plus word lengths.

This operation requires some 64 word times, plus the initial four minimum word times required for phases l through 4, or approximately 18 msec.


Fig. 20.6. Drum timing signals.

Machine Timing. There are several timing tracks permanently recorded on the drum. These are used to generate various timing and gating signals that occur within a word time.

The first line of Fig. 20.6 shows the clock or bit pulses. These pulses occur at a rate of 120,000 per second. The second line shows a signal occurring at the sign digit position. Whenever it is desired to define the existence of the sign of a word, say in the accumulator, the coincidence of this signal and the output of the accumulator loop will produce the needed information.

A third track on the drum defines the various sectors around the drum. On this track are permanently recorded sequential numhers of the 64 sectors around the drum. As actually utilized, the numbers on this track represent the next sector that will pass under the head. A fourth track is used to define the bits where the sector part of the address occurs.

A fifth track defines where the channel part of the address occurs, and a sixth defines where the order bits occur.

Address Selection. It was discussed above how, in phase 2, the command word was read from the memory into the instruction register. Previous to this it was necessary to select the proper track and sector defining the location of this word.

Given in the counter register is the address of this new command. This word is circulating in synchronism with all the information on the drum and in particular with the timing tracks. First the timing signal from track 4 is gated with the output of the counter register. This selects out the correct 5 bits to send to the track-selection register, which in turn selects the correct head.

At the same time the timing signal from track 4 is used to gate information from track 3 and the counter register, The contents of these bits from the counter register are compared with the output of track 3. If they compare exactly, then the next sector, the start of which is defined by track 2, is the desired one and thus contains the new command word. This word is then gated to the instruction counter.

If a coincidence is not found a comparison is made during the correct bits of the next sector. This continues until the correct sector is found.


Fig. 20.7. Sector interlacing LGP-30.

Sector Interlacing. The sector addressing around the drum is such that there are 9 sectors between successive addresses. This is shown in Fig. 20.7. Assuming a command in sector 00, the operand search begins during sector 57 time. The operand may be located in any of the words associated with sectors 50, 43, 36, 27, 22, or 15. The search for the next command begins at sector 08 so that the next command that is located in 01 will be read without delaying a drum revolution.

This procedure can take place for all those commands which require only the first four program periods. Thus execution time including access can be as low as 2 msec.

Equipment. The computer uses a total of 110 vacuum tubes and 1,400 diodes. The power requirement is 1.5 kw at 115 volts alternating current.

Auxiliary Equipment. A Flexowriter is used as input-output. This is a combination typer and paper-tape reader-perforator. Since the registers are dynamic they are not readily displayable, An oscilloscope is provided to view the contents of the three registers.


Fig. 20.8. LGP-30 block diagram.

Fig. 20.9. Bendix G-15 diagram (Courtesy of Bendix Corp.)

20.4.3. The Bendix G-15 Computer. Memory. The memory of the Bendix G-l5 computer is a magnetic drum. The main memory consists of 20 tracks with 108 words in each. There is a 16-word high-speed memory in the form of four tracks with four words each. The arithmetic circuits involve four tracks, three with two words and one single-word register. Another single-word register is used in the control circuits and there are timing tracks on the drum.

As indicated in Figs. 20.9 and 20.11 the G-15 has a source-destination structure (see See, 20.2) and the command essentially specifies the source and destination involved and the time at which transfer is to occur. In order to provide for minimum access for commands, each command also specifies the time at which the next command is to be read from memory.

All tracks in the memory recirculate, making it possible to transfer information from any track to any other track. In terms of Fig. 20.9 there are direct connections (not shown) from each read head to the corresponding write head, 2.

Inverting Gates. All transfers of information are via the inverting gates (8 of Fig. 20.9) and under control of parts of the command (CH and S/D of 7 of Fig. 20.11). During such transfers the sign bit may be deleted (absolute value), the number may be complemented if negative, or the sign may be changed and then complemented if negative. All these operations may be done on the basis of single precision (29-bit numbers) or double precision (58-bit numbers).

Arithmetic Operations. The arithmetic circuits include three two-word registers and a single one-word register. One of the two-word registers and the single-word register have addition circuits associated with them. Thus there are two independent accumulators, one for single-length words and one for double-length words. Multiplication and division as well as shifting are done in the two-word registers. Under control of the command any number of digits in thc multiplier may he used or any number of digits in a quotient may be developed. The particular arithmetic operation to he done depends only upon source and destination values of the command being executed.


Fig. 20.10. Bendix G-15 command cycle (Courtesy of Bendix Corp.)

Input and Output. One of the 108-word memory lines serves as a buffer register in the input and output process. Inputs and outputs are initiated by the control circuits upon the execution of the appropriate command. Input terminates upon reception of a STOP code from the input device. Output terminates after a few characters under format control or after larger numbers of words when the buffer empties. Thus the maximum number of words which can be handled as a block on input or on output is 108 words.

Input is from the typewriter and a photoreader which reads punched paper tape. Output is to the typewriter and to punched paper tape. Auxiliary equipment provides communication to and from magnetic tape and punched cards.

Once an input or output process has been initiated the computer may continue with the program. The program may test for the termination of an input or output process in order to know when input information may be used.

The Command Cycle. The command circuits usually pass through four states illustrated in Fig. 20,10. The states are (1) READ COMMAND, (2) WAIT TO TRANSFER, (3) TRANSFER, and (4) WAIT TO READ NEXT COMMAND. The WAIT periods are caused by the cyclic nature of the memory. Note that in the case of "immediate" commands the WAIT TO TRANSFER period may be by-passed. Immediate commands may transfer for any number of word times up to a maximum of 108.

Precession. Figure 20.11 shows that information from the source passes through the "early bus" to the inverting gates and through the "intermediate bus" to a box where there is a possibility of the information passing through the one-word AR register before arriving on the "late bus." Under control of one command as many as 108 words may he transferred in this way and the effect is to displace all the words one word position. In other words, their sector location has been increased by unity or their address has been increased by one.


Fig. 20.11. Bendix G-15 transfer system.

There are precession circuits associated with the input and output buffer which give precession by four bits or by four words. These operations can be programmed to occur anytime and not just during an input or output process.

The Digital Differential Analyzer Attachment. An attachment to the G-15 may be had which converts part of the computer into a digital differential analyzer (see Sec. 19). This conversion uses part of the memory and does not interfere with the operation of the general-purpose computer. This makes it possible to control the integrations going on in the DDA "on the fly," so to speak. For example, it is possible to change the system of equations being integrated without interrupting the integration process.